1. Field of Invention
Embodiments of the invention generally relate to memory management in computing systems. More specifically, at least one embodiment relates to apparatus, systems and methods for memory management to support memory pages that have a plurality of page sizes.
2. Discussion of Related Art
Accessing memory (for example, to write data to or read data from memory) requires accurate identification of the locations within the physical memory. Because today's processing systems rely on multitasking to run many applications at the same time, memory management schemes employ virtual memory. The virtual memory is an address space created by the processing system for one or more tasks. The processing system then correlates locations in virtual memory to the corresponding locations in the associated physical memory of the system, for example, address locations in RAM. This translation (or mapping) occurs whenever data is read from or written to the physical memory. Because address translation is so widely used in processing operations, approaches have been implemented in an effort to make the preceding as efficient as possible.
A technique referred to as “paging” is often employed where a virtual memory is used to access the pages of the physical memory. According to this approach, a virtual address identifies a specific location in the physical memory. A page table is employed to map the virtual address to addresses in the physical memory. For example, the virtual address can include at least an identification of the correct page table and location in the page table that includes the physical address of a page of physical memory. The process of identifying the correct entry in the page table is sometimes referred to as “indexing.” Each of the entries in the page table is associated with an offset field that includes a specific location (for example, a byte) within the page of physical memory.
The page table structure for a given application is established based on the size of the pages of the physical memory. Often the physical memory includes more than one page size. However, the page table structure for a given virtual memory address format is fixed. As a result, for a physical memory that includes more than one page size, the page table structure is established based on the smallest size of a page in the physical memory.
According to this approach, a single entry in the virtual memory is sufficient to map a given location of a small page in the physical memory and all addresses within the small page. However, it is necessary to use multiple entries in a page table to map all of the virtual addresses required for the larger page sizes of the physical memory because of their increased size. The result is that duplicate entries appear in the page table for each of the large pages, respectively, where these duplicate entries are each associated with different offsets.
Referring now to FIG. 1, an approach 100 is illustrated in which a single page size is used in a page table 102 of virtual memory to support a physical memory that includes two page sizes; a small page size 106 and a large page size 108. The virtual addresses 110, 114 for both small pages and large pages include a virtual page number field (111, 115) and an offset field (112, 116). For the small page size, the virtual page number field 111 alone provides a page entry field 118 used to identify an entry 104 in the page table. The offset field 112 for the small page size need only identify a location of the associated page of physical memory. Thus, a single page entry in the page table is employed for all locations for a given small page.
The size of the virtual address for small and large pages is the same and the page entry field is also the same size for both page sizes. However, the offset field for large pages is larger than the offset field for small pages because there are more address locations (for, example, bytes) in the large pages. Thus, the page entry field 120 for large pages requires information in the virtual page number field 115 and information in the offset field 116. In the illustrated example, the most significant bit(s) 117 of the offset field are included as the least significant bit(s) in the page entry field 120. That is, the page entry field directly extends from the virtual page number field 115 into the offset field 116. The preceding approach results in each of the multiple entries which are required for a large page being located consecutively in the page table because adjacent addresses differ by a single least significant bit.
The multiple entries for the larger page size in the page table provide duplication that is only necessary where two page sizes are used because the duplicate entries for a given page refer to the same address in the physical memory. Often, different page sizes are only needed for some processing while during other operations the page table 102 is employed with only a single page size. However, prior approaches do not organize page table entries in a manner that easily allows consolidation of the page table entries with the removal of duplicate entries. In FIG. 1, for example, where the page table includes entries for multiple large pages, the entries for the various large page sizes are distributed throughout the page table and the entries for the same large page are clustered together. In practice, this combination of an inconsistent distribution of entries for large pages and clustering for the same page is inefficient because it does not allow for an easy reduction in the size of the page table where for example all the entries are for large pages. The manner in which entries in the page table are indexed contributes to the problems with prior approaches.
A translation lookaside buffer (TLB) is employed to improve the speed at which a virtual address is mapped to an address in the physical memory of the processing system. In general, the TLB is a cache that stores the translation of an address in virtual memory to a corresponding address in the physical memory. Typically, the TLB includes translations for those addresses that are used most frequently and/or most recently. The use of the TLB increases the speed at which commands are executed because a memory operation can proceed without a search of the page table where the address translation is identified in the TLB.